The invention relates to microcomputers and computer systems and to methods of operating such.
Computer systems may incorporate a processor with a plurality of other devices which may generate signals for transmission to the processor or other devices. Such signals may include interrupt request or control signals for a CPU or memory access operations. The sources and destinations of such interdevice signals may be numerous requiring complex interconnections or control systems to permit the source and destination of such signals to communicate.
It is an object of the present invention to provide an improved computer system and method of operating a computer system in which signals may be distributed as addressed packets on an address and data path particularly in a system involving at least two interconnected chips.
The invention provides a computer system comprising two interconnected chips each having an on-chip address and data path, a CPU arranged to send and receive addressed packets on the path and at least one module with event circuitry to generate addressed event request packets for distribution on the path, the paths on the respective chips being interconnected through respective external ports on each chip so that addresses on each of the paths form part of a common address space addressable from either chip.
Preferably each chip includes a plurality of modules other than said CPU each connected to the address and data path with a respective on-chip address and each having packet generating circuitry to generate an event request packet including a destination address.
Preferably each chip includes a memory interface as well as an external port, each connected to said address and data path and each having a respective on-chip address.
Preferably said CPU and module each have packet generating circuitry arranged to provide in a request packet a destination address identifying a selected chip within the system as well as a selected address on the address and data path of the selected chip.
Preferably the CPU and module, or modules, of each chip include packet generating circuitry responsive to receipt of a request packet to generate an addressed response packet for distribution on said address and data path.
Preferably the CPU and at least one other module include packet generating circuitry arranged to produce memory access packets as well as event request packets.
Preferably the CPU and at least one module on each chip includes packet generating circuitry arranged to provide in the packet the address of the module or CPU acting as the source of the packet as well as providing the destination for the packet.
Preferably the packet generating circuitry of the CPU is responsive to receipt of a request packet to determine from the packet a source address of the packet and to generate a response packet using said source address as the destination indicator for the response packet.
Preferably said at least one module on each chip is arranged to provide an interrupt request packet including a priority indicator for the interrupt request, said CPU including comparator means for determining the priority of the request on receipt of the packet.
The invention includes a method of operating a computer system comprising two interconnected chips each having an on-chip address and data path, a CPU and at least one module, said method comprising generating addressed event request packets for distribution on the address and data path, each request packet including a destination address for the packet, the address space allocated for a destination address being commonly addressable from either chip so that packets generated on one chip may be distributed through respective external ports to a location on the address and data path of the other chip.
Preferably the CPU on each chip is arranged to allocate an address to each request packet which identifies both the destination chip as well as the destination location on the address and data path of the destination chip.
Preferably the or each module generating an addressed event request packet includes in the destination address an identifier for the selected destination chip as well as an address on the address and data path of the selected destination chip.
Preferably the creation of a request packet on one chip for transmission to a destination on another chip includes obtaining an address translation indication to provide the selected address for both the destination chip and the required destination location on that chip.
Preferably the CPU and at least one module on each chip responds to receipt of a request packet by generation of a response packet for distribution to the source of the request packet.
Preferably the address and data path of each chip is used for distributing addressed event request packets and addressed response packets between chips as well as the distribution of memory access packets to a memory interface on each chip.
Preferably said event request packets include requests of two types, a first type forming prioritised interrupt request packets and a second type comprising control command packets.